发明名称 RECORDER FOR SUPERVISING CONTROL STATE
摘要 <p>PURPOSE:To obtain both the short-time data and the rough long-time data by recording the data obtained in a prescribed sampling cycle and the data obtained for each integer multiple of said sampling cycle after combining them. CONSTITUTION:The memory is stopped after 0.5sec for the data obtained by a sensor 2 in the 5mS sampling cycle when an abnormality detector 31 detects that a controller has the abnormality. Under such conditions, the data obtained at the time points preceding by 1sec and after 0.5sec respectively can be stored in a memory area 32 as long as a memory area 32, for example, can store the data of 1.5sec. Furthermore the data are stored in a memory area 34 by a counter 33 with the data accuracy, i.e., once per 100 times. This memory is stopped hereafter when 5sec passed if the output signal is delivered from the detector 31. Then the data obtained in 50sec before occurrence of a trouble and in the following 5sec are stored in the area 34 as long as this area 34 can store the data equivalent to 55sec.</p>
申请公布号 JPS62109104(A) 申请公布日期 1987.05.20
申请号 JP19850248873 申请日期 1985.11.08
申请人 HITACHI LTD;HITACHI TECHNO ENG CO LTD 发明人 KOTAKE KAZUYOSHI;OZAWA TSUTOMU;KURIHARA HIROYUKI
分类号 B60L3/12;G05B23/02 主分类号 B60L3/12
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