| 摘要 |
<p>An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters (10i1, 10i2) arranged in a particular configuration wherein the individual arbiters are located according to their relative priority. Each arbiter has a request terminal (REQ) for receiving access request signals, requesting access to a shared system bus, and an enable terminal for receiving an enabling signal. The enabling signal is generated if access requests are not received by higher arbiters in the particular configuration relative to the specific arbiter. If an arbiter is energized by coincidence of an access request signal and an enabling signal, an access grant signal is developed. If more than one access request signal energizes the arbiter at the same time, a command rotor (10i1b, 10i3b), connected to the arbiter, determines the priority of access of the request signals to the shared bus in response to the "rotation" of the command rotor. If the access request signal is of a predetermined type, a pre-emptive grant signal may be developed from its arbiter even in the absence of an access request if there are no higher requests and no lower grants. If a refresh request is received by an arbiter when its enabling signal is not received, the refresh request is latched, and a refresh takes place when the enabling signal is finally generated. </p> |
