发明名称 DETECTING SYSTEM FOR ABNORMALITY OF RANDOM ACCESS MEMORY
摘要 PURPOSE:To eliminate the need for a battery power supply which is needed for storage of data stored in a parity bit RAM by setting the correct parity value to this RAM after reading out the data contents of the RAM for all spaces of the RAM immediately after a power supply is applied. CONSTITUTION:An initial parity generating circuit 20 reads out the contents of a RAM 12 immediately after a power supply is applied to a computer main body 1. Based on this readout data, the correct parity bit data is calculated and then written on a parity bit memory RAm 14. This action is carried out for all spaces of the RAM 12. Thus it is possible to detect completely the abnormality of the RAM 12 with no battery protection secured for the contents of the RAM 14.
申请公布号 JPS62109146(A) 申请公布日期 1987.05.20
申请号 JP19850249995 申请日期 1985.11.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 FURUKUBO YUJI
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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