| 摘要 |
PURPOSE:To halve the maximum sum total of variation components of electric current flowing to bus signal lines by inverting and outputting the logic state of signals when the combination of the logic states of signal line groups satisfies prescribed conditions. CONSTITUTION:A majority decision circuit 1 decides the logic states of N pieces of signals X1-XN to be led to a bus. Then '0' and '1' are outputted as a control signal C if the number of '0' is less than N/2 and larger than N/2+1 among those signals X1-XN. These signals X1-XN are inverted by an EX-OR gate 2 only when the signal C is set at '1' and turned into signals Y1-YN to be sent to a bus together with the signal C. At the receiver side, the received signals Y2-YN are inverted by an EX-OR gate 3 only when the signal C is equal to '1'. Thus signals Z1-ZN are obtained. Thus the number of signal lines which are equal to '0' is set at N/2 at the maximum among those signals Y1-YN.
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