发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent power consumption from increasing and an abnormal operation such as a latchup from occurring by providing an impurity region in a shape for surrounding an anode region between the anode region and a P-type insulating region to sufficiently reducing hFE of a parasitic PNP transistor having the anode region as an emitter, a cathode region as a base and the P-type insulating region as a collector. CONSTITUTION:A high density N-type buried region 12 and an N-type epitaxial region 13 are formed on a P-type substrate as an N-type cathode region, a P-type region formed on the surface of the region 13 is formed as a P-type anode region 14, the cathode region is surrounded by a P-type insulating region 15, and a P-type region 16 is formed in a shape for surrounding the anode region between the anode region and the region 15. The region 16 can be formed simultaneously with the region 14. hFE of a parasitic PNP transistor can be remarkably reduced effectively by providing the region 16, the ratio of a current which flows to a P-type substrate region can be reduced from the anode current of a CB bonding diode.
申请公布号 JPS62109353(A) 申请公布日期 1987.05.20
申请号 JP19850250217 申请日期 1985.11.07
申请人 NEC CORP 发明人 NAKASHIBA HIROSHI
分类号 H01L27/06;H01L21/8222;H01L29/861 主分类号 H01L27/06
代理机构 代理人
主权项
地址