发明名称 SIMULATION METHOD FOR LOGIC CIRCUIT
摘要 PURPOSE:To attain the simulation of a logic circuit without adding any conversion to a test program for the limit of a test subject range, by using a logic circuit model formed with a basic logic element only for the machine word instruction group deseired to calculate the detailed simulation result of the logic circuit. CONSTITUTION:A logic circuit model 1 uses a basic logic element that has the low simulation speed of a logic circuit but can calculate the detailed working process of the logic circuit. While a logic circuit model 2 has a high simulation executing speed for the logic circuit and calculates the working process of the logic circuit only with the component element of the logic circuit which can be operated by a machine word instruction. Then the model 2 performs the execution of the machine word instruction for both the initialization part and the result deciding part of a test program. Then the model 1 carries out the execution of the machine word instruction to be tested when the model 2 recognizes said instruction given previously from outside.
申请公布号 JPS62109136(A) 申请公布日期 1987.05.20
申请号 JP19850248806 申请日期 1985.11.08
申请人 HITACHI LTD 发明人 HONMA KAZUYUKI;KATO ZENTARO;ONIZUKA NOBUHIKO
分类号 G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/25
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