| 摘要 |
PURPOSE:To obtain the absolute value of a difference between a minuend and a subtrahend without requiring any timing control by providing the first and the second adding circuits and a selecting circuit for selecting their outputs. CONSTITUTION:A binary value which has been applied to minuend input terminals 1-4 is inputted to A3-A0 terminals of an adding circuit 18, and also to A3-A0 terminals of an adding circuit 19 after having been converted to a complement on one by inverter circuits 13-16, respectively. In the same way, a binary value which has been applied to subtrahend input terminals 5-8 is inputted to B3-B0 terminals of the circuit 19, and also to B3-B0 terminals of the circuit 18 through inverter circuits 9-12, respectively. A carry-in input terminal 17 is fixed to '0'. In this case, when a minuend is smaller than a subtrahend, a complement of the absolute value of a difference is obtained in an output of S3-S0 terminals of the circuit 18, and a carry-out signal 61 is not outputted. ON the other hand, when the former is larger, a one's complement of the absolute value of a difference is obtained in S3-S1 terminals of the circuit 19, a carry-out signal 62 is not outputted, and also, when both are equal, both the circuits provide an output in the same way. A selecting circuit selects a circuit in accordance with each output, and outputs the absolute value of a difference. |
