High-speed full differential amplifier with common mode rejection

摘要

A high speed low power linear two micron CMOS full differential operational amplifier has a pair of output cascode stages each providing a respective differential output with rejected common mode signals. The amplifier comprises an input differential amplifier stage driving a pair feedback current mirror loads each cross connected to the pair of cascode output stages providing the differential outputs. Current domain operation provided by current mirror arrangements enables fast operation of the full differential amplifier. Each output cascode stage comprises four stacked transistors including two signal transistors and two dynamically biased pass transistors. The feedback current mirror loads and the cascode output stages provide the amplifier with single gain stage respecting each differential output thereby reducing the need for large compensation capacitors while improving the dynamic range of the two differential outputs. The gain of amplifier is ninety decibels with a frequency bandwidth of fifty megahertz and with low power dissipation at two milliwatts. The amplifier also comprises two feedback differential stages receiving a single combined common mode signal formed from the two differential outputs. Each feedback differential stages then drives a respective pair feedback current mirror loads which provide negative feedback signals to the output cascode stages whereby common mode signals are rejected at the differential outputs.