| 摘要 |
PURPOSE:To attain the multiplication of a desired weight without skipping the titled counter circuit by constituting the titled counter circuit with a counter, a status decoder and a reset signal synchronizing circuit receiving a status signal and an external reset pulse and generating the internal reset pulse thereby applying reset at an optional and desired count status. CONSTITUTION:An external reset pulse 3 is fed to a reset signal synchronizing circuit 7, while a status signal 6 from a status decoder 5 is fed to the circuit 7, and a prescribed logic processing is applied between the signals. It is possible to constitute the reset signal synchronizing circuit 7 by a two-input AND gate circuit, and in this case, two inputs are ANDed and an internal reset pulse 8 is generated. The external reset pulse 3 goes to logical 1 before and after the presence of the count status '3' and its state is kept, and the count output by output pulses 4a-4c from the counter 1 is decoded sequentially by the status decoder 5, and when a desired count status is decoded, the level of the status signal 6 goes to logical '1'.
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