发明名称 ALL-ZERO DETECTING CIRCUIT FOR DECIMAL ARITHMETIC RESULT
摘要 PURPOSE:To detect early the occurrence of an all-zero state of the decimal arithmetic result by securing a constitution substantially equal to the all-zero detection of the binary arithmetic result. CONSTITUTION:An intermediate sum arithmetic circuit of each digit gives information to an all-zero deciding circuit part 2 in case '9' or '0' is obtained in the hexadecimal expression. Based on said information, the circuit 2 obtains an equation 1 in the form of conditions A showing alphaNOT ALL-ZERO', and decides the conditions showing 'ALL-ZERO' by the inverse of A which means NOT A. Thus the constitution that is substantially equal to the circuit constitution for detection of all-zero in a binary arithmetic mode. Thus the detection of all-zero is carried out easily in a decimal arithmetic mode.
申请公布号 JPS62106541(A) 申请公布日期 1987.05.18
申请号 JP19850246804 申请日期 1985.11.02
申请人 FUJITSU LTD 发明人 KOMATSUDA HIROSHI
分类号 G06F7/50;G06F7/494 主分类号 G06F7/50
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