| 摘要 |
PURPOSE:To decrease parasitic capacity and to reduce power consumption by preventing an input rejected by the 2nd succeeding stages from being applied to the initial stage by a gate circuit. CONSTITUTION:Gate circuits G0-G7 are connected to the input sides of the 2st selecting stages S00-S03 of a signal selecting circuit and the outputs of the gate circuits A0-A3 and inputs do-dn are inputted to the circuits G0-G7. Further, a next stage S20 is connected to the output sides of the respective stages S00-S03 through the 2nd output stages S10 and S11. The circuits A0-A3 and inverters I0 and I1 constitute a decoder circuit and inputs a1-a3 are decoded to apply outputs a00, a01, a10, and a11 to the circuits G0-G7. Further, the respective inputs a1-a3 are supplied to FETs of the respective stages S00-S03, S10, and S11, and next stage S20. Then, the circuits A0-A3 and G0-G7 prevent inputs which are rejected by the 2nd and succeeding stages from being inputted to the selecting means S00-S03.
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