发明名称 MULTIPROCESSING SYSTEM
摘要 PURPOSE:To multiplex the double control circuit by providing the double control circuit at the sharing memory interface or respective computers, controlling respective sharing memory controller of two pairs of the memory unit in the sharing memory device and executing the double control. CONSTITUTION:A sharing memory interface 44-1 has double port interfaces 71a and 71b corresponding to sharing memory ports 34a-1 and 34b-1 of a sharing memory device 30 and a system bus interface 72 corresponding to a system bus 43-1. The port interfaces 71a and 71b and the system bus interface 72 are mutually connected by an internal bus 73, and to the internal bus 73, a double control circuit 74 to execute the double control is connected. The sharing memory interface 44-1, further, connects a microprocessor 75 to control the double control circuit 74 and the same microprocessor 75 to the internal bus 73. Thus, the system has a microcomputer interface 76 to be able to control the double control circuit 74.
申请公布号 JPS62103755(A) 申请公布日期 1987.05.14
申请号 JP19850242616 申请日期 1985.10.31
申请人 TOSHIBA CORP;TOSHIBA ENG CO LTD 发明人 SAKO SHOJI;NAKAJIMA YUTAKA;SHIDA KOJI;OOYAMA AKIHIKO;TAKEMOTO HIDEJI
分类号 G06F15/167;G06F12/16;G06F15/16 主分类号 G06F15/167
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