| 摘要 |
PURPOSE:To obtain a minute configuration without tapered parts on the side wall of a gate layer, by forming a composite metal layer on a compound semiconductor substrate, forming a resist-layer coating, providing a hole at a position where the gate layer is to be formed, oxidizing an exposed titanium layer, and performing ion beam milling with the titanium layer as a mask. CONSTITUTION:Si ions are implanted in a specified region of a GaAs semiinsulating substrate 1. A channel part, which is an N-type low concentration region, is formed. On this part, a Ti-W layer 2, an Mo layer 3, an Au layer 4 and a Ti layer 5 are deposited (a). The Ti layer 5 is coated with positive resist 6 (b). then a hole part 7 is provided in the resist 6 at a gate-electrode forming position, and a part of the Ti layer 5 is exposed (c). Then ultraviolet rays generating O3 is applied on the exposed Ti layer 5, and a titanium oxide layer 8 is formed. When the positive resist layer is dissolved and removed, a pattern is obtained with the titanium oxide layer 8 as a mask (d). The Au layer 4 and the Ti layer 5 in the composite metal layer is removed by ion milling in an Ar atmosphere. With the Ti-Au as a mask, the Mo layer 3 and the TiW layer 2 are removed by an RIE method. Thus the gate layer having a line width of 0.25Xm is obtained (e).
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