| 摘要 |
PURPOSE:To prevent the second sense amplifier from being operated faster than a timing by providing a switching means which equalizes the potential of each bit wire in a pair of bit wires and that of the second sense amplifier driving signal wire to the half of the write voltage of a bit of memory cell information. CONSTITUTION:Transistors 8i1 and 8i2 for transferring a MOSFET of P-channel are provided between the driving signal wire 12 of a sense amplifier 10 and a bit wire, the inverse of BLi, and an equalize signal, the inverse of phiP is given to the gates of the 8i1 and 8i2, a conduction with a low level being generated. Also, transistors 8i3 and 8i4 for transferring a MOSFET of N-channel are provided between a driving signal wire 13 and the bit wire, the inverse of BLi, and the equalize signal phiP is given to the gates of the 8i3 and 8i4, a conduction with a high level being generated, and each anti-ground electrostatic capacity of bit wires the inverse of BLi and BLi and driving signal wires 12 and 13 are equalized. Thereby, it is prevented that the second sense amplifier is operated faster than an initial timing.
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