Circuit arrangement for clock recovery

摘要

The described circuit arrangement for clock recovery has a pulse former stage on the input side, the output of which is connected to one input of a gate, while the other input of the gate is activated by an evaluation circuit of a counter. The counter is timed by a clock source whose frequency is higher than the frequency of the clock which is to be recovered, the counter controlling the evaluation circuit and being reset by the output signal of the gate. In order to avoid all possible counter reset errors and to produce a clock which is virtually jitter-free, it is provided to design the evaluation circuit as a decoding matrix which converts the counter reading into a binary signal with which the gate is opened for a predefined sequence of counter readings, to use as a clock source the voltage-controlled oscillator of a phase-locked loop whose input for the control parameter is connected to the output of the gate and to tap the recovered clock from the output of a frequency divider whose input is connected to the output of the voltage-controlled oscillator.