发明名称 PARALLEL/SERIAL CONVERTER
摘要 PURPOSE:To obtain a series output from a data selector by starting reading data with an optional data number without being affected by a ratio of parallel- serial conversion. CONSTITUTION:Data are outputted from the output terminal 8 of a shift register successively as shown in figure (b) in synchronism with clock pulses supplied to shift registers 6 and 9 in common. At this time, data outputted from respective parallel output terminals 111-114 of the shift register 9 are delayed by one clock pulse period. Namely, data #0 is outputted from the terminal 111 with a clock pulse #5, and data #0 is outputted from the terminal 112 with a clock pulse #6; and data #0 is outputted from the terminal 113 with a clock pulse #7, and data #0 is outputted from the terminal 114 with a clock pulse #8. A clock pulse #8 and succeeding pulses correspond to an effective operation period. Namely, data having an optional data number are obtained at parallel output terminals 111-114 at the same time with the clock pulse #8 and succeeding pulses.
申请公布号 JPS62104322(A) 申请公布日期 1987.05.14
申请号 JP19850244822 申请日期 1985.10.31
申请人 YOKOGAWA MEDICAL SYST LTD 发明人 ISHIGURO SHINICHI;KONDO KAZUAKI;SAKAMOTO TOMOSADA
分类号 H03M9/00 主分类号 H03M9/00
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