| 摘要 |
PURPOSE:To reduce the chip area as the whole of the device and reduce the cost by a method wherein a memory cell is composed of three elements an MOSFET, resistor, and gated junction element. CONSTITUTION:The MOSFET31 is constructed with an n<+> type diffused region 42 as the drain or source, an n<+> type diffused region 43 as the source or drain, and an insulation gate electrode 44 as the gate. The gated junction element 33 has the p-n junction constructed by the region 43 and a p type semiconductor substrate 41 and the gate constructed by part of a wiring 45. The load resistor 32 is constructed by a high resistant wiring part 47. A word line WL is composed of the electrode 44, and a bit line BL is composed of a wiring 48. |
