Aligned interconnections between logic stages.

摘要

A layout for random logic in which different stages (e.g. 88, 90) are assigned to columns according to the flow of logic signal. Each stage may consist of several parallel logic blocks defining a logic function and having an output. The logic blocks are implemented by several diffusion areas, not necessarily contiguous. The output line (102, 104) of a logic block is aligned vertically to match one or more gate electrodes (64) of following stages that it drives. The inter connection to the following stages can be implemented by a single horizontal polysilicon line (108) which also functions as the gate electrodes (64). The breaks in the diffusion of a logic block can accomodate the passage of polysilicon lines (112) not being used in that logic block.