| 摘要 |
A high speed monolithic current switching digital-to-analog converter (DAC) is provided. The DAC includes input level shift clock and data drivers (401, 421), differential dual latches (403, 405), differential multiplexers (409) and high speed current switching cells (411). Utilizing complementary clocks at one-half the input data rate, data is effectively latched at each transition or edge of the clock pulse rather than at only the positive (or negative) going edge of the clock. Thus, feedthrough of the previously unused clock edge and perturbation in the DAC output caused by the unused clock edge is eliminated. |
