| 摘要 |
PURPOSE:To increase the capacity of the cell part of the IC to be used for memory as well as to enable the transistor of circumferential circuit to perform a high speed operation by a method wherein the junction depth of the cell part is formed in the depth with which it comes in contact with the high density region layer in the substrate, and the junction depth of the circumferential circuit part is formed as shallow as possible. CONSTITUTION:B<+> ions are implanted in a P type Si substrate 11, and a high impurity layer region 12 is formed. A gate oxide film 15 is formed by performing a P<+> ion implantation 13 for channel stopper and a field oxidation 14, and a patterning is performed by growing a phosphorus-doped polysilicon. The width of the gate polysilicon 16 of the transistor on a cell part is made wider than the width of the gate polysilicon 17 of the transistor. A diffusion layer 19 is formed by performing a P<+> ion implantation, and a source and drain region 18 of the circumferential circuit part is formed by implanting As<+> ions. As the diffusion layer 19 and the high density impurity region 12 are closely formed each other, the width of a depletion layer is narrow, the capacity of the cell part is made larger, and the strength for the soft error due to alpha rays is increased, and the capacity of the circumferential circuit part is made small because its junction depth is shallow, thereby enabling to perform a high speed operation. |
