发明名称 SHARED INPUT/OUTPUT SYSTEM
摘要 PURPOSE:To increase the number of CPUs which share input/output equipment and to reduce the size of hardware by connecting the respective CPUs to a common high-speed serial bus which is branched from system control buses of the plural CPUs through interface devices. CONSTITUTION:The interface devices 51-1-51-3 are connected to the system control (SC) buses 41-1-41-3 of the CPUs 40-1-40-3 respectively. Then, the interface devices 51-1-51-3 are connected to the high-speed serial (S) bus 61 in common and decentralized processors (DCP) 71-73 which control unshown input/output equipment are connected to this S bus 61. Consequently, the CPUs 40-1-40-3 share the input/output equipment through the corresponding interfaces 51-1-51-3, common S bus 61, and DCPs 71-73, so even if the number of the CPUs increases, the DCPs need not be altered.
申请公布号 JPS62102348(A) 申请公布日期 1987.05.12
申请号 JP19850242218 申请日期 1985.10.29
申请人 TOSHIBA CORP;TOSHIBA ENG CO LTD 发明人 SAKO SHOJI;NAKAJIMA YUTAKA;JINBO YASUSHI;UMEDA KENICHI;NAKAMURA MITSUHIRO
分类号 G06F13/36;G06F13/12;G06F13/38;G06F15/16;G06F15/17;G06F15/173 主分类号 G06F13/36
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