| 摘要 |
PURPOSE:To attain a low power consumption by providing a power source control circuit at every section obtained by putting together plural columns in a memory cell array and reducing a bit line current with respect to a nonselected section. CONSTITUTION:N-sections are constructed with M-columns in the memory array as one section, source terminals of drive transistors Q3 and Q4 for each memory cell 5 are connected to voltage converting circuits 301-30N. If a section selection signal SS1 selects the circuit 301, its output node 30'is set to a ground ing potential. When the circuit 301 is not selected, the output node 30' is set to an inbetween of a power source potential VDD and the grounding potential. In terms of a nonselected section the bit line current passing a bit line load circuit 6 a bit line BL or an inversion BL the transistor Q3 or Q4 is reduced to decrease power consumption.
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