发明名称 INPUT CIRCUIT FOR ADDITION/SUBTRACTION COUNTER
摘要 PURPOSE:To attain accurate count even with duplicated simultaneous input by storing an addition input and a subtraction input in a storage means temporarily both in two-way when they are inputted simultaneously and inputting one advanced input to a delay circuit via a gate circuit. CONSTITUTION:When the addition input A and the subtraction input B are inputted with a minute time difference, the signal inputted later is stored in flip-flop circuits 1, 2, the signal inputted earlier is used for count and after it is finished, the count is executed by using the other stored input signal. Thus, even when the addition input A and the subtraction input B are inputted simultaneously, when either input appears at one output of NAND circuits 3, 4 due to the difference in wiring or variation of the characteristic of the flip-flop circuits 1, 2 and the NAND circuits 3, 4, since the other input is kept waiting at the next moment, the accurate count processing is applied by the said timewise operation. That is, since the response of the NAND circuits 3, 4 is very quick, the proper processing is applied.
申请公布号 JPS62101125(A) 申请公布日期 1987.05.11
申请号 JP19850239532 申请日期 1985.10.28
申请人 KOYO DENSHI KOGYO KK 发明人 GOTO YUICHI
分类号 H03K21/02;H03K23/00;H03K23/86 主分类号 H03K21/02
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