发明名称 PROCESSING SYSTEM FOR MAIN MEMORY ACCESS
摘要 PURPOSE:To secure the advantages of a memory element having a fast access time by stoting previously a memory flag indicating an access mode into a memory constituting an address conversion mechanism. CONSTITUTION:A memory 2 is retrieved by 5-9 bits of a real address 1 to obtain a physical address that gives an access to a main memory. Then the segment number of an access subject is read out together with an upper address within the segment and a memory flag for selection of an access mode. The lower addresses within a segment formed by 10-25 bits of the address 1 are combined with the upper addresses within said segment for decision of the address within the segment. Then an access is given to the corresponding physical address. In this case, the specific access time is instructed by said memory flag read out of the memory 2.
申请公布号 JPS62100850(A) 申请公布日期 1987.05.11
申请号 JP19850241021 申请日期 1985.10.28
申请人 FUJITSU LTD 发明人 TAKAHASHI MASANORI
分类号 G06F12/10;G06F12/02;G06F12/06 主分类号 G06F12/10
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