| 摘要 |
<p>PURPOSE:To suppress the jitter of an internal timing lower by controlling a reset reversible counter to be reset so as to restore the count to a reference value thereby ensuring the set bit control. CONSTITUTION:A reception data IN2 including jitter and an internal timing IN1 are fed to the 1st temporary storage circuit 5 via input terminals 20, 30, and whether the signal is retarded or advanced is subjected to sampling detection and the result is stored tentatively. The output signal of the circuit 5 and a reception signal being the result of retarding the data IN2 at a delay circuit 10 are subjected to an operating processing by the 1st NAND circuit 11 and fed to a reset reversible counter 6. When the count reaches a preset bit number, the NAND condition is established in a NAND circuit 12 to generate an output signal. The output signal presets the 2nd temporary storage circuit 2 of the post-stage. Thus, the set bit control is executed surely and the jitter of the internal timing IN1 is suppressed lower.</p> |
