| 摘要 |
PURPOSE:To simplify the counter control circuit by stopping count tentatively only when a counter read request exists and restarting the count after a time required to read the count elapses. CONSTITUTION:When a counter read request exists, a counter read request signal is turned on for one system clock. Then a non-inverting output of a FF1 is turned on and an inverting output is turned off in the next system clock. Thus, a binary counter 2 executes no count and since an output of the FF1 is turned on, a read register 4 reads the count of the binary counter 2. That is, since the binary counter 2 stops the count by one system clock each when the counter read request exists, a count error is generated in a strict sense. So long as the titled circuit is not applied to a circuit requiring a frequent count read request, however, the accuracy sufficient practically is attained.
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