| 摘要 |
PURPOSE:To improve the dielectric strength characteristic between the gain and drain by providing an enhancement MOS transistor (TR) whose gate is connected to a power supply and a depletion MOS TR connected between a gate of a field relaxing MOS TR and the power supply. CONSTITUTION:The field relaxing MOS TR Q13 is provided between a MOS TR Q8 and a node N4 and MOS TRs Q14, Q15 are provided between the gate of the TR Q13 and the power supply VDD. The gate of the MOS TR Q14 is connected to the power supply VDD and an input signal phiin is fed to the gate of the MOS TR Q15. Further, enhancement type is adopted for MOS TRs Q1-Q14 and depletion type is adopted for the MOS TR Q15. The 1st and 2nd MOS TRs apply conduction control of the field relaxing MOS TR and the provision of the TR Q13 prevents the potential decrease of the threshold voltage component at charging of the node N4. Thus, the dielectric strength characteristic between the gate and drain of the MOS TRs is improved. |
