| 摘要 |
PURPOSE:To shorten the access time and simplify the manufacturing process, by using an FET for the load of a memory cell and controlling the gate potential of the FET with an output of a driving circuit of a word line. CONSTITUTION:Two units of double-emitter transistors Q1 and Q2 with the bases and collectors connected crossing to each other are used, and one emitter is connected to the bit line BL. The memory cell MC is formed by connecting each collector to the word line WL via a load constisting of the junction-type FETLT1 and LT2. The line WL is driven by one output of the driving circuit DC consisting of the ECL formed with the transistors Q11 and Q12 on the output stage of the row address decoder. Then the gate potential is controlled by the supplement output of other side of the circuit DC for the load transistors LT1 and LT2 of the cell MC. |
