| 摘要 |
PURPOSE:To count sequentially the number of '1's or '0's during a prescribed count section by providing an up-down counter using an output of a counter as a periodical load value and employing an up-count clock and a down-count clock so as to apply counting. CONSTITUTION:The titled circuit consists of a control circuit 3 generating an up-count clock and a down-count clock through the combination of an output of a delay circuit 1 and a data input and the up-down counter 4 using the output of the counter 2 as a periodic load value and employing the up-count clock and the down-count clock to actuate counting. An AND gate generates the up-count clock when a data before one count section is '0' and the present data is '1' and generates the down-count clock when the data before one count section is '1' and the present data is '0'. No up-count clock nor down-count clock is generated when the data before one count section is '0' and the present data is '0' or the data before one count section is '1' and the present data is '1'. |
