发明名称 PRIORITY CONTROL SYSTEM FOR PACKET
摘要 <p>PURPOSE:To decrease the delay in exchange for a specific packet by providing a priority polling means for applying an optional number of times of pollings to the 3rd FIFO memory connected to the 1st path connected to the 1st FIFO memory to which a specific incoming communication line is connected at each polling. CONSTITUTION:While a sequential polling means 101 in the 1st transfer circuit (incoming transfer circuit) applies an optional number of times of pollings sequentially to each 1st FIFO memory connected to the 1st transfer circuit, a priority polling means 102 applies an optional number of times of pollings to the 1st FIFO memory to which a specific incoming communication path is connected at each polling. Similarly, a priority polling means 104 of the 2nd transfer circuit (outgoing transfer circuit) applies an optional number of times of pollings to the 3rd FIFO memory connected to the 1st path connected to the 1st FIFO memory connecting a specific incoming communication path at each polling of a sequential polling means 103. Thus, the polling frequency to the 1st and 3rd FIFO memories connected between a specific incoming communication path and an output communication path is increased to decrease the waiting time thereby reducing the delay in exchange.</p>
申请公布号 JPS6298940(A) 申请公布日期 1987.05.08
申请号 JP19850239064 申请日期 1985.10.25
申请人 FUJITSU LTD 发明人 TSUTSUI HIDEKAZU;TOMINAGA SUSUMU;SAKAKAWA KAZUO
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