发明名称 |
Semiconductor delay line for logic circuit |
摘要 |
The main subject of the invention is a semiconductor delay line for logic circuit. The invention relates mainly to a delay device including elementary operators inducing a delay increment. The total delay is equal to the delay induced by an elementary operator multiplied by the number of elementary operators through which the signal passes. The invention applies mainly to the production of delay lines. <IMAGE>
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申请公布号 |
FR2589651(A1) |
申请公布日期 |
1987.05.07 |
申请号 |
FR19850016388 |
申请日期 |
1985.11.05 |
申请人 |
INFORMATIQUE MILITAIRE SPAT AERO |
发明人 |
MICHEL BERTHE ET BERNARD JAMIN-BIZET;JAMIN-BIZET BERNARD |
分类号 |
H03K5/13;H03K5/15;(IPC1-7):H03H11/26 |
主分类号 |
H03K5/13 |
代理机构 |
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主权项 |
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地址 |
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