| 摘要 |
<p>PURPOSE:To facilitate the adjustment of timing as compared with when performing the high speed clock operation of a total indication time and to simplify the configuration of a control circuit, by delaying the greater part of an indicated time by a clock obtained by normalizing an input clock on a N-bit basis and delaying only a fraction time overflowed from normalization by high speed clock operation. CONSTITUTION:A delay time is normalized on an N-bit basis by a delay circuit 3 inputting a receiving time reference signal 101, a delay time indicating signal 102 and a clock signals, and a timing signal 103 delayed by the normalized time from a reference signal 101 is outputted. This signal 103 is applied to a data generating circuit 5 and a time difference correction indicating circuit 4 and the output signal 105 from the circuit 5 is applied to a transmission timing correction circuit 7. The delay time difference of the signal 103 and the indicating signal 102 is calculated by the correction indicating circuit 4 and a correction indicating signal is applied to the transmission timing correction circuit 7. Only a fraction time overflowed from normalization is delayed by high speed clock operation and the timing adjustment of the transmission data signal 107 is facilitated.</p> |
