| 摘要 |
<p>As the 8-bit input signal applied to a threshold device (50) reaches a first threshold level, the 1-bit output signal changes from a logical zero to a logical one. The 1-bit output signal is delayed by one system clock period and fed back. The delayed 1-bit output signal is combined (40) (e.g., merged or added) with the 8-bit input signal, and the resulting signal is applied to the threshold device to provide a hysteresis feature. Once the delayed 1-bit output signal becomes a logical one, the input signal has to drop below a second, lower threshold level before the 1-bit output signal can revert back to a logical zero, whereby a margin of noise immunity is provided.</p> |
