| 摘要 |
<p>PURPOSE:To prevent generation of a DC component by adding a signal inverted at the period of 2.5 bits to a modulation signal formed by converting bit values 0 and 1 of a data series into a binary code comprising 00,10 and 01,00 in response to the preceding bit value. CONSTITUTION:An address signal and mode control signal to a buffer memory 1 to which a data bit is inputted at a prescribed period are outputted from a control section 2 by a clock C1, the data is read one by one bit and read out. An output of the buffer memory 1 is subjected to multiplexing 4 by an output from a ROM of a data generating circuit 5 and the result is inputted to an M<2> recording bit generating circuit 6, the bit values 0 and 1 are converted into the binary code comprising 00,10 and 01,00 in response to the preceding bit value and the result is inputted in parallel with a shift register 7. A serial output from the register 7 and a gate signal 9 are ANDed (8) and an inverted write signal corresponding to 2.5-bit width is obtained from an exclusive OR gate 10 and an FF 11. Thus, the generation of the DC component is prevented and sure synchronization is obtained.</p> |
