发明名称 A clamping circuit for an analogue to digital converter.
摘要 <p>The clamping circuit clamps a threshold of an ADC to a signal level just below the black level of a television signal. …<??>During the blanking period, a negative-going peak is superimposed on the input signal to produce the waveform 76. Each time this crosses the 0000,0001 threshold of the ADC, the polarity of the output of a comparator changes (see the middle waveform). The comparator compares the ADC output and a reference value. …<??>The input signal is biased according to the integral of the comparator output. When signal levels are stable, the comparator output is symmetrical, its integral is zero and no change occurs in the biassing. …<??>If signal levels drift, the negative going peak crosses the threshold for the second time relatively sooner or later. The comparator output becomes assymmetric and has a non-zero integral. Consequently, the biassing level changes to compensate for the drift.</p>
申请公布号 EP0220894(A2) 申请公布日期 1987.05.06
申请号 EP19860308073 申请日期 1986.10.17
申请人 RANK CINTEL LIMITED 发明人 MILLWARD, JOHN DAVID;BROWN, KEVIN DAVID
分类号 H03K5/00;H03K5/08;H03M1/00;H04N5/18;(IPC1-7):H03M1/00 主分类号 H03K5/00
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