| 摘要 |
<p>PURPOSE:To obtain a master/slave type flip-flop provide with a clock synchronization reset without adding an external circuit, by inserting and connecting a transfer gate to an input side of an inverter, and connecting a control signal of the transfer gate to a control signal of a transfer gate being in an output side of the inverter. CONSTITUTION:When a two-input NOR gate 19 and a transfer gate 20 are inserted and connected, a master/slave type flip-flop provided with a clock synchronization reset is obtained. An R-S flip-flop is constituted of an inverter 16 and the two-input NOR gate 19, and since a control signal of the transfer gate 20 is the same clock signal CK as a control signal of a transfer gate 13, an input reset signal R is held in said R-S flip-flop until an input data D is read. Accordingly, a pulse width of the reset signal R comes to have no relation to a pulse width of the clock signal CK, therefore, the sensitive capacity of a reset operation is improved.</p> |
