| 摘要 |
<p>Multiplying circuit for multiplying a first signal x(t) by a periodic second signal y(t) and being particularly suitable for use as an amplitude demodulator in a stereo decoder or in a phase-locked loop. It comprises N signal channels 26(k) wherein k=0, 1, . . . n-1, each receiving the first signal x(t) and each producing a channel signal. Each signal channel is formed by, arranged in cascade, a switched-capacitor circuit 28(k;1), 28(k;2), 29(k), the circuit included in the signal channel being controlled by a train of control pulses g(k,i) which each have a finite duration and occur with a repetition period To and at instants to+k(To/N)+iTo where i= . . . -2, -1, 0, 1, 2, 3, . . . , means 29(k), 31, 30 for multiplying the amplitude of the signal x(t) by a constant weighting factor W(k) which is equal to y(to+k(To/N), pulse-reshaping means 29(k), 30, 31 for converting a pulse applied thereto into a pulse having a predetermined duration. The channel signals thus obtained are added together in an adder device 30, 31 to form a sum signal. This sum signal is sampled in a sampling arrangement 34(1), 34(2), 35 at instants comprised within the interval between the end of a control pulse g(k,i) and the beginning of the subsequent control pulse g(k+1,i).</p> |
