| 摘要 |
The coder described exhibits three analog input filters by means of which coarse filtering of the three components is carried out. The input filters are followed by analog-digital converters followed by digital chips by means of which further filtering and a reduction in the word clock rate are carried out. The filtered and word-clock-rate-reduced components are supplied to a recoding unit which combines them to form a 2-Mbit/s signal. The measures described save filtering means. In the case where the three components of the video signal are already present in digital form, they are fed, after changing the word clock rate and after filtering, into the signal path which consists of all the units following the analog/digital converters.
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