| 摘要 |
A programmable logic array is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates having latched complementary outputs. The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine. |
