| 摘要 |
PURPOSE:To always improve the operating frequency by using a gate circuit to forma carry-out signal to a higher order side than plural Q outputs and forming a carry-in signal from the gate circuit by the carry-out signal from all lower-order counter ICs. CONSTITUTION:NAND gates 2a-2d go to an L level when both outputs Q3, Q0 are at an H level. Then in case of a 16-bit count 000FH, only the output 14 of the gate 2d goes to an L level. Since L and H levels are given respectively to Cin terminals of counters IC1c, 1d and 1a, 1b, when one pulse of a system clock 10 is inputted, the counter IC1c, 1d are incremented and the counter IC1a, 1b are latched. When 15 pulses of clocks 10 are inputted incrementally, the value as the 16-bit counter is 001FH. The operation above is repeated and when the value goes to 00FFH, outputs 13, 14 of the gates 2c, 2d go both to L and outputs 11, 12 of the gates 2a, 2b go both to H. When one pulse of the pulse 10 is inputted, the value of the 16-bit counter is 0100H. |
