| 摘要 |
A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.
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