发明名称 FORMING METHOD FOR CAPACITY OF SEMICONDUCTOR MEMORY CELL
摘要 PURPOSE:To readily form a semiconductor memory cell having an Hi-C structure by bonding spin ON glass layers having a P-type impurity and an N-type impurity of different diffusing speeds in a groove, and simultaneously diffusing to form the P-type first diffused region and the N-type second diffused region. CONSTITUTION:A groove 2 is formed on a negative conductivity type semiconductor substrate 1, a P-type silicon semiconductor substrate 1 is covered with a silicon oxide film 3 and a CVD silicon nitride film 4, the substrate 1 formed with the prescribed groove 2 is exposed, anisotropically etched by RIE to form the groove 2. A glass layer 5 containing a reverse conductivity type impurity to the negative conductivity type impurity having different diffusing speed is bonded to the substrate 1 including the groove 2. The P-type and N-type impurities are simultaneously diffused to the side of the groove 2 to form the first and second diffused regions 6, 7. A thin insulating film 8 is formed on the groove 2, a cell-plate electrode 9 is formed on the film 9, and the transistor of a semiconductor memory cell is formed.
申请公布号 JPS6292461(A) 申请公布日期 1987.04.27
申请号 JP19850233829 申请日期 1985.10.18
申请人 SANYO ELECTRIC CO LTD 发明人 TANAKA TSUNEO
分类号 H01L27/04;H01L21/822;H01L21/8242 主分类号 H01L27/04
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