| 摘要 |
PURPOSE:To simplify circuit constitution and to suppress the power consumption by providing a capacitor and a means charging the capacitor periodically to a watchdog timer circuit, a means discharging the capacitor and a means detecting a voltage across the capacitor and generating a control signal. CONSTITUTION:The timer circuit consists of a capacitor C1, PMOS and NMOS transistors (TRs) Q1, Q2, a comparator 1, a reference voltage source 2 and a one-shot pulse generator 13. The TRs Q1, Q2 charge/discharge the capacitor C1 in response to a low and a high level of a signal IDD. The signal IDD goes to a low level in case of, e.g., an NOOP instruction and inverted to a high level when the instruction differs from the NOOP instruction. Then a program is programmed so that the NOOP instruction is executed until a voltage VN across the capacitor C1 is not smaller than a reference voltage V0. If program runaway takes place, the voltage VN is finally smaller than the reference voltage. As a result, the program runaway is detected by a comparator 1. A pulse generator 13 generates a reset pulse RS in response to an output VC of the comparator 1. The pulse RS resets a program counter 3. |
