发明名称 FRAME ALIGNER CIRCUIT
摘要 <p>PURPOSE:To prevent increase of the scale of hardware by making a write counter and a read counter operate to become 1 period by 2n bits, and making the phase of an output signal of the read counter change by n bits when the phase of output signals of the write counter and read counter draws near. CONSTITUTION:The circuit has a memory 10 having a capacity of 2n bits. In this case, period of operation of a write counter and a read counter is made 2n bits, the phases of output signals of the write counter and read counter are compared to detect approach of phases, and when the phases got near, the phase of output signals of the read counter is varied by n bits.</p>
申请公布号 JPS6286935(A) 申请公布日期 1987.04.21
申请号 JP19850226424 申请日期 1985.10.11
申请人 NEC CORP 发明人 YOSHIMOTO KOJI
分类号 H04L7/00;H04Q11/04 主分类号 H04L7/00
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