Via formation for multilayered metalization

摘要

A process for enhanced formation of vias in multilevel conductive structures for integrated circuit devices. A semiconductor wafer, bearing a multilayered first level metalization characterized by a tungsten alloy top layer, is annealed in a suitable ambient so as to form a distinctly colored superficial film atop the first level metalization. The interlevel dielectric is then deposited and subsequently selectively dry etched until the film becomes discernible, the film itself serving as an etch stop so as to protect the top layer of the first level metalization. Exposed portions of the superficial film are then removed through a standard plasma etch step. Remaining areas of the film promote intimate binding between the first level metalization and the interlevel dielectric.