发明名称 |
Semiconductor memory device having divided regular circuits |
摘要 |
In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P1 to P16).
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申请公布号 |
US4660174(A) |
申请公布日期 |
1987.04.21 |
申请号 |
US19840625682 |
申请日期 |
1984.06.28 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAKEMAE, YOSHIHIRO;NAKANO, TOMIO;SATO, KIMIAKI |
分类号 |
H01L21/822;G11C5/02;G11C5/14;G11C11/401;H01L21/60;H01L27/04;H01L27/10;(IPC1-7):G11C5/00 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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