| 摘要 |
PURPOSE:To make the operation test of a parity check circuit itself simple by including instructions for controlling a flip-flop in a program. CONSTITUTION:Lines excepting one bit line in a data bus 3 are directly connected to the input of a parity check circuit 2 and the one bit line is connected to the input of the parity check circuit 2 through an EOR gate 7. Output of an RS flip-flop (FF) 11 is connected to another input of the EOR gate 7. The FF 11 is set and reset by the output of two address decoders (AD) 12, 13 operated by the program processing of a computer. When making operation test, the FF 11 is set through the AD 12 and '1' is inputted to the EOR gate 7. Then, bits inputted to the EOR gate out of data to be tested are inverted and inputted to the parity check circuit 2, and tested whether the circuit 2 detects it correctly or not. |
