发明名称 METHOD FOR INVESTIGATING STATE OF LOGICAL CIRCUIT
摘要 PURPOSE:To enable the certain investigation of a state, by simple constitution such that the output of a logic circuit is collated with the trouble investigating data read from a memory to control the address stepping of the memory. CONSTITUTION:The outputs SIG0-SIG3 of a logic circuit are collated with trouble investigating data DATA0-DATA3 from a memory 6 in the corresponding logic parts 1(0)-1(3) of an input pattern detection part 1. The outputs of said logical parts 1(0)-1(3) are subjected to AND processing by an AND circuit 2 and, on the basis of the AND result, the stepping of an address is performed by an address counter stepping part 3 and a counter 5 to perform the reading accessing of the memory 6. After the same collation was repeated, the finish of the test is displayed on a display part 6 through an input pattern detection confirming signal DET. Therefore, by altering the memory content of the memory 6, the state investigation of various logic circuits is certainly performed by simple constitution.
申请公布号 JPS6283675(A) 申请公布日期 1987.04.17
申请号 JP19850225215 申请日期 1985.10.09
申请人 FUJITSU LTD 发明人 KOIKE TAKASHI
分类号 G06F11/22;G01R31/28 主分类号 G06F11/22
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