| 摘要 |
<p>PURPOSE:To reduce power consumption without changing a maximum delay time and to speed up the operation without changing power consumption by equaling the timing of an address signal inputted to a decoder circuit irrespective of the length of wiring from an address gate to the decoder circuit. CONSTITUTION:Wiring lengths to a decoder driver 2 from plural address gates A, B, C, F and G satisfy a<b<c<f<g. Assuming that the average resistance value of the address gate A remains unchanged in order to flow a current amount in proportion to the wiring length, the average resistance value of the address gate G is made lower, and the others are set to the average resistance value in proportion to a parasitic capacity between them, every access time becomes the same as that of the gate A, and the actin is speed up. Assuming that the average resistance value of the address gate G remains unchanged, that of the gate A is made larger, and the others are set to the average resistance value in proportion to a parasitic capacity between them, all the current values can be constant, and the access times can be equal, thereby reducing power consumption.</p> |
