| 摘要 |
PURPOSE:To prevent the increase in the impedance of a line while decreasing the length of a power line and to prevent generation of an output waveform distortion attended with a folded mechanism by applying folded constitution to a continuous pattern by the multi-stage connection of CMOS gate circuits. CONSTITUTION:Small chips 20 shown in paper-tablet are individual CMOS gate circuits in a chip pattern, each column 22 is constituted by connecting odd number of CMOS gate circuits 20 longitudinally, the columns are connected to the next column at the edge while being folded to constitute the continuous pattern of one delay circuit as a whole. Through the adoption of the folded structure, it is possible to oppose power lines (VDD, VSS) interdigitally as comb- line shape thereby decreasing the adverse effect on the increase in the impedance of the power line possibly. Further, each column is constituted by an odd number of CMOS gate circuits, then the cause of variation in the delay time produced at the folded parts is canceled together effectively, the leading and trailing delay times are made equal as the entire circuit to prevent generation of the output waveform distortion. |
